EFM32G-DK3550【PDF 371/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

26.4 Register Map

The offset register address is relative to the registers base address.

Offset

Name

Type

RW

R

RW

RW

RW

R

W1

W1

RW

RW

W

RW

RW

Description

Control Register

Status Register

Channel 0 Control Register

Channel 1 Control Register

Interrupt Enable Register

Interrupt Flag Register

Interrupt Flag Set Register

Interrupt Flag Clear Register

Channel 0 Data Register

Channel 1 Data Register

Combined Data Register

Calibration Register

Bias Programming Register

26.5 Register Description

26.5.1 DACn_CTRL - Control Register

Offset

0x000

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:22

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

21:20

REFRSEL

0x0

RW

Refresh Interval Select

Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in

DACn_CHxCTRL is set.

Value

0

1

2

3

Mode

8CYCLES

16CYCLES

32CYCLES

64CYCLES

Description

All channels with enabled refresh are refreshed every 8 prescaled cycles

All channels with enabled refresh are refreshed every 16 prescaled cycles

All channels with enabled refresh are refreshed every 32 prescaled cycles

All channels with enabled refresh are refreshed every 64 prescaled cycles

19

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

18:16

PRESC

0x0

RW

Prescaler Setting

Select clock division factor.

Value

PRESC

Description

Clock division factor of 2^PRESC.

2011-04-12 - d0001_Rev1.10

371

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